When the model meets the design requirements, you then generate VHDL ®, Verilog ® or SystemVerilog code that implements the design. You can simulate and synthesize the generated HDL code by using industry-standard tools, and then map your system designs on FPGAs and ASICs.
https://www.mathworks.com/help/hdlcoder/ug/introduction-to-stateflow-hdl-code-generation.html

